A new and fast approach to very large scale integrated sequential circuits test generation
Abstract
We present a new approach to automatic test pattern generation for
very large scale integrated sequential circuit
testing. This approach is more efficient than past test generation methods,
since it exploits knowledge of potential circuit defects.
Our method motivates a new combinatorial optimization problem,
the Tour Covering Problem.
We develop heuristics to solve this optimization
problem, then apply these heuristics as new test generation procedures.
An empirical study comparing our heuristics to existing methods
demonstrates the superiority of our approach, since our approach
decreases the number of input vectors required for the test,
translating into a reduction in the time and money required
for testing sequential circuits.
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- A new and fast approach to very large scale integrated sequential circuits test generation (37 pages, 229 KB)
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- Dorit S. Hochbaum and Jennifer Adams. Operations
Research, 45:6, 842-856, (1997).
dorit@hochbaum.ieor.berkeley.edu
7/30/98